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Application Note 1081
500kHz to 1MHz. The PG_PWM output indicates loss of
regulation on the PWM output.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. The error amplifier sets the
threshold for the PWM comparator. The high side switch is
turned off when the sensed inductor current reaches this
threshold. After a minimum dead time, preventing shoot
through current, the low side N-channel MOSFET will be
turned on and the current ramps down again. As the clock
cycle is completed, the low side switch will be turned off and
the next clock cycle starts.
The control loop is internally compensated, reducing the
amount of external components. The PWM section includes
an anti-ringing switch to reduce noise at light loads.
The switch current is internally sensed and the minimum
current limit is 550mA.
Frequency Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to the SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1MHz. The device
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch over will be initiated if no rising edge
on the SYNC pin is detected for a duration of two internal
1.3μs clock cycles.
PWM Soft Start
As the EN_PWM (Enable) pin goes high, the soft-start
function will generate an internal voltage ramp. This causes
the start-up current to slowly rise preventing output voltage
overshoot and high inrush currents. The soft-start duration is
typically 5.5ms with 750kHz switching frequency. When the
soft-start is completed, the error amplifier will be connected
directly to the internal voltage reference. The SYNC input is
ignored during soft start.
Power Good (PG_PWM)
When the chip is enabled, this output is HIGH when V OUT is
within 8% of 1.8V and active low outside this range. When
the PWM is disabled, the output is active low. PG_PWM is
the complement of PG_PWM.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4 bit up/down
counter counts up two LSB. Should it not be in overcurrent
the counter counts down one LSB (but the counter will not
5
"rollover" or count below 0000). If >33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the softstart counter is
reset. After 16 clocks the PWM output is enabled and the SS
cycle is started.
If V OUT exceeds the overvoltage limit for 32 consecutive
clock cycles, the PWM output is shut off and the SS counters
reset. The softstart cycle will not be started until EN or V IN
are toggled.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, dual-mode
comparator and internal feedback voltage divider.
The band gap reference is connected to the error amplifier ’s
inverting input. The error amplifier compares this reference
to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower than the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output. The output voltage is fed back through an
internal resistor divider connected to V OUT1 /V OUT2 pins.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V max. It goes to the active low state if either
LDO output is out of regulation by more than 15%. When the
LDO is disabled, the output is active low.
Internal P-Channel Pass Transistors
Both ISL6413 LDO Regulators feature a typical 0.5 ?
r DS(ON) P-channel MOSFET pass transistor. This provides
several advantages over similar designs using PNP bipolar
pass transistors. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably. PNP
based regulators waste considerable current in dropout
when the pass transistor saturates. They also use high base
drive currents under large loads. The ISL6413 does not
suffer from these problems.
Integrator Circuitry
Both ISL6413 LDO Regulators use external 33nF
compensation capacitors for minimizing load and line
regulation errors and for lowering output noise. When the
output voltage shifts due to varying load current or input
voltage, the integrator capacitor voltage is raised or lowered
to compensate for the systematic offset at the error amplifier.
Compensation is limited to ±5% to minimize transient
overshoot when the device goes out of dropout, current limit,
or thermal shutdown.
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